| OBJECTIVE: | Seeking a position in the computer industry in any of the following fields:
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| EDUCATION: | Carnegie Mellon University, Pittsburgh, PA MS Electrical and Computer Engineering Master of Science GPA: 3.3 Carnegie Mellon University, Pittsburgh, PA BS Electrical and Computer Engineering and Computer Science Bachelor of Science GPA: 3.3 |
| SPECIAL SKILLS: | Rapid ramp-up on new tools, inherited code, and changes in project goals and
time lines Programming: C/C++, IA32 assembler, UNIX shell, Java, Verilog HDL, Visual Basic-Excel Operating Systems: Windows, various UNIX's, DOS, Mac OS Software: Cadence Verilog, Magic, SPICE, Visual C++, Excel, Word |
| 01/2004 - Present | Intel Corporation, Austin, TX - Senior Researcher Own modifications to an existing performance model to evaluate design decisions. Investigating new, high performance microarchitectures for IA32. Interacting with logic and circuit designers to guide microarchitecture decisions. Received Division Recognition Award for work relating new process techniques to future microarchitectures. |
| 01/2001- 12/2003 | Intel Corporation, Austin, TX - Researcher Developed new, high performance microarchitectures for the Itanium architecture. Designed and implemented a new performance model to evaluate design decisions. Interacted with logic and circuit designers to guide microarchitecture decisions. Received three Division Recognition Awards relating to development of this microarchitecture, simulation of same, and correlation effort to existing products. |
| 01/1999-12/2000 | Intel Corporation, DuPont, WA -Design Engineer Took charge of a performance and functional model of chipset hardware, added features and fixed bugs. Part of the team validating performance and functionality of the E8870 chipset for servers and workstations. |
| 6/1998-9/1998 | Intel Corporation, Hillsboro, OR - Graduate Intern Added functionality to an existing place and route tool. Worked with development team to define interface and goals. Validated functionality and performance of modified tool. |
| PATENTS AND PUBLICATIONS: | Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, Bryan Black, Hierarchical
Scheduling Windows, International Symposium on Microarchitecture 35, pp. 27-
36. 10 patents filed, 2 inventions in defensive publications. |
| REFERENCES: | Available upon request |